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1 NWK933 NWK933 3.3v 10/100 fast ethernet transceiver to mii features l integrated 10/100 mbps ethernet in a single chip solution l single 3.3v power supply l half duplex and full duplex in both 10base-t and 100base-tx l full mii for a glueless mac connection l extended register set l integrated 10base-t transceivers and receive / transmit filters l integrated adaptive equaliser and base line wander correction (for fddi killer packet) l full auto-negotiation support for 10base-t and 100base-tx both half and full duplex l link status change interrupt l parallel detection for supporting non auto negotiation in legacy link partners l low dynamic current l deep sleep low power mode <1ma l internal power on reset l 64 pin 1mm thick tqfp package l single magnetics for 10base-t and 100base-tx operation for a single rj45 connector l support for flow control 802.3 specification l integrated 6 led driver ds5029 issue no 2.1 may 1999 odering information NWK933/cg/tp1n description the NWK933 is a single chip 3.3v cmos physical layer solution from mii to the magnetics. it is designed for 10base-t and 100base-tx ethernet, based on the ieee 802.3 specifications. the NWK933 is compatible with the auto negotiation section of ieee 802.3u and provides all the support needed for the 802.3 full duplex specification. rj45 switch or mac NWK933 isolation magnetics figure 1 system block diagram l low external component count l loop-back mode for diagnostics l intelligent power management (auto shutdown, auto wake) l low transmit jitter
2 NWK933 figure 2pin connections tp64 48 mint 47 dvdd3 46 mdc 45 mdio 44 dgnd3 43 refclk 42 oscvdd 41 xtal1 40 xtal2 39 oscgnd 38 txgnd4 37 txvdd4 36 txref100 35 txref10 34 txvdd3 33 txgnd3 subgnd1 32 pa0 31 pa1 30 pa2 29 txon 28 txvdd1 27 txgnd1 26 txgnd2 25 txvdd2 24 txop 23 anen 22 rxvdd1 21 rxin 20 rxip 19 rxgnd1 18 pa3 17 rxgnd2 16 rxvdd2 15 resetn 14 pa4 13 spdst 12 fdst 11 rxgnd3 10 rxvdd3 9 dvdd1 8 colst 7 actst 6 lnkst 5 tx_en 4 dgnd1 3 tx_er 2 subgnd2 1 64 tx_clk 63 tx03 62 txd2 61 txd1 60 txd0 59 rx_er 58 rxd3 57 rxd2 56 rxd1 55 rxd0 54 dvdd2 53 rx_clk 52 dgnd2 51 rx_dv 50 crs 49 col functional description the NWK933 has three basic modes of operation: 10base-t, 100base-tx and low power modes. the control block is designed to manage these modes by starting and stopping the 10m and 100m transceivers in a well-controlled manner such that no spurious signals are output on either the mii or twisted-pair interfaces. furthermore, it continuously monitors the behaviour of the transceivers and takes corrective action if a fault is detected. other modes described herein are repeater mode and reset mode. 25mhz reference clock the NWK933 requires a 25mhz +/-100ppm timing reference for 802.3 compatible operation. this may be supplied either from the integrated oscillator or from an external source. when the integrated oscillator is used, a suitable crystal must be connected across the xtal1 & xtal2 pins (see external components) and refclk must be tied low. when an external source is used, it must be input to the refclk pin and xtal1 must be tied low. xtal2 must be unconnected. 10base-t operation 10mb/s data transfer on the mii 10mb/s data is transferred across the mii with clock speeds of 2.5mhz. the mac outputs data to the NWK933 via the mii interface, on the txd[3:0] bus. this data is synchronised to the rising edge of tx_clk. to indicate that there is valid data for transmission on the mii, the mac sets the tx_en signal active. this forces the NWK933 device to take in the data on the txd[3:0] bus. this is serialised and directly encoded as manchester data, before being output on the txop/ txon differential output for transmission through 1:?2 magnetics and onto the twisted-pair. the transmit current is governed by the current through the txref10 pin, which must be grounded through a resistor as described in external components. rx10 clock recovery the NWK933 employs a digital delay line controlled by the 100mhz synthesizer dll to derive a sampling clock from the incoming signal. the recovered clock runs at twice the data rate (nominally 20mhz). when a signal is received from the signal detect block, it is used to strobe link pulses and manchester encoded serial data.
3 NWK933 the manchester data stream will be decoded into a 4- bit parallel data bus, rxd[3:0]. the rxd bus is clocked out on rx_clk rising. the NWK933 must detect the first 4 bits of pre-amble before rx_dv is set high. when rx_dv is high, any manchester coding violation will set rx_er high. rx_dv is reset by a continuous sequence of zeroes, or by the end-of-packet idle terminator (11 11 00 00). whilst rx_dv is low, the data is invalid. 100mhz synthesizer this synthesizer employs a delay-locked loop (dll) to generate a 100mhz timing reference from the 25mhz reference clock. this 100mhz reference is used by the 10base-t transmit and receive functions and is divided by 5 to provide a 20mhz data strobe. the 20mhz clock is used to derive the 2.5 mhz tx_clk in 10base-t mode. the synthesizer is disabled when not in 10base-t mode. tx10 pulse shaper & filter the pulse shaper & filter employs a digital finite impulse response filter (fir) to pre-compensate for line distortion and to remove high frequency components in accordance with the 802.3 standard. the pulse shaper & filter is disabled when not in 10base-t mode. tx10 latency when connected to appropriate magnetics the latency through the tx10 path is less than 2bt (200ns) for data transmissions. this timing is measured from the rising edge of tx_clk to the output of the transmit magnetics. the tx10 path will not transmit up to the first two manchester encoded bits of a data transmission, as permitted by the 802.3 standard . rx10 filter & rx10 signal detect these blocks work in unison to remove noise and to block signals that do not achieve the voltage levels specified in 802.3. signals that do not achieve the required level are not sampled in the clock recovery block and are not passed to the outputs. rx10 latency when connected to appropriate magnetics the latency through the rx10 path is less than 6bt (600ns). this timing is measured from the input of the receive magnetics to the rising edge of rx_clk. the rx10 path may ignore up to three manchester encoded bits at the start of data reception (802.3 allows up to 5 bits). 100base-tx operation 100mb/s data exchange on the mii interface 100mb/s data is transferred across the mii with clock speeds of 25mhz. the mac outputs data to the NWK933 via the mii interface, on the txd[3:0] bus. this data is synchronised to the rising edge of tx_clk. to indicate that there is valid data for transmission on the mii, the mac sets the tx_en signal active. this forces the NWK933 device to take in the data on the txd[3:0] bus and replace the first octet of the mac preamble with start-of-stream delimiter (ssd) symbols to indicate the start of the physical layer stream. when the data transfer across the mii is complete, the mac deasserts the tx_en signal and the NWK933 adds end-of-stream delimiters (esd) symbols onto the end of the data stream. the complete data stream (the physical layer stream) is encoded from 4 bits into 5 bits, scrambled, converted to mlt3 and driven to the txop and txon pin differentially. the tx100 path is disabled when not in 100base-tx mode and, with the exception of the rx100 signal detect, the rx100 receive path is disabled when not in 100base-tx mode. 125mhz synthesizer this synthesizer employs a phase-locked loop (pll) to generate a 125mhz timing reference from the 25mhz reference clock. this 125mhz reference is used by the 100base-tx transmit function and is divided by 5 to provide a 25mhz data strobe on tx_clk. tx_clk is frequency and phase locked to the 25mhz reference with a small phase offset. the synthesizer is disabled when not in 100base-tx mode.
4 NWK933 tx100 piso, encoder and scrambler data from the mii is loaded into the tx100 piso, encoder and scrambler on the rising edge of tx_clk. it is converted to serial mlt3 for outputting to the tx100 driver. the txd[3] bit is output first. the piso & encoder do not operate until the 125mhz synthesizer is locked to the 25mhz reference. this avoids transmission of spurious signals onto the twisted-pair. tx100 driver the tx100 driver outputs the differential signal onto the txop and txon pins. it operates with 1:root 2 magnetics to provide impedance matching and amplification of the signal in accordance with the 802.3 specifications. the transmit current is governed by the current through the txref100 pin, which must be grounded through a resistor as described in external components. the tx100 driver is disabled in 10base-t mode and in loop back mode.if no data is being transmitted from the mac, the NWK933 outputs idle symbols of 11111 (suitably scrambled). tx100 latency the transmit latency from the first tx_clk rising when tx_en is high to the first bit of the j symbol on the cable is 8bt. rx100 equalizer & base-line wander correction the rx100 equalizer compensates for the signal attenuation and distortion resulting from transmission down the cable and through the isolation transformers. the equalizer is self-adjusting and is designed to restore signals received from up to 10db cable attenuation (at 16mhz). when the equalizer is active it adjusts to the incoming signal within 1ms. thereafter, the equalizer will continuously adjust to small variations in signal level without corrupting the received data. the 100base-tx mlt3 code contains significant low frequency components which are not passed through the isolation transformers and cannot be restored by an adaptive equalizer. this leads to a phenomenon known as base-line wander which will cause an unacceptable increase in error rate if not corrected. the NWK933 employs a quantized feedback technique to restore the low frequency components and thus maintain a very low error rate even when receiving signals such as the killer packet described in the tp_pmd spec. rx100 clock recovery the rx100 clock recovery circuit uses a phase- locked loop (pll) to derive a sampling clock from the incoming signal. the recovered clock runs at the symbol bit rate rate (nominally 125mhz) and is used to clock the mlt3 decoder and the serial to parallel converter (sipo). the recovered clock is divided by 5 to generate the receive clock (rx_clk) which is used to strobe received data across the mii interface. when no signal is detected in 100base-tx mode, the pll is locked to the reference clock and runs at 125mhz. this ensures that rx_clk runs continuously at 25mhz in 100base-tx mode. when a signal is present, the clock recovery pll remains locked to the reference until the equalizer has adjusted, then it requires up to 1ms to phase lock to the incoming signal. no data is passed to the mii interface until lock is established. rx100 sipo, decoder and descrambler the rx100 sipo, decoder and descrambler convert the received signal from serial mlt3 to 4-bit wide parallel receive data on the mii. this appears on the rxd[3:0] bus which is clocked out on the falling edge of rx_clk. when a frame starts the NWK933 decodes the ssd symbols and then asserts the rx_dv signal, in order to inform the mac that valid data is available. when the NWK933 detects the esd, it deasserts the rx_dv signal. rx100 latency the latency from the first bit of the j symbol on the cable to crs assertion is between 11 and 15bt. the latency from the first bit of the t symbol on the cable to crs de-assertion is between 19 and 23bt. 100mb/s transmit errors if the NWK933 detects that the tx_er signal has gone active whilst the tx_en signal is active, then it will propagate the detected error onto the cable by transmitting the symbol 00100 . figure 3 shows the meaning of the different states of tx_en and tx_er. tx_er is sampled inside the NWK933 on the rising edge of tx_clk.
5 NWK933 100mb/s receive errors when there is no data on the cable, the receiver will see only the idle code of scrambled 1s. if a non idle symbol is detected, the receiver looks for the ssd so that it can align the incoming message for decoding. if any 2 non consecutive zeros are detected within 10 bits, but are not the ssd symbols a false carrier indication is signalled to the mii by asserting rx_er and setting rxd[3:0] to 1110 whilst keeping rx_dv inactive. the remainder of the message is ignored until 10 bits of 1s are detected. if any data is decoded after a ssd which is neither a valid data code nor an esd, then an error is flagged by setting rx_er active whilst the rx_dv signal is active. this also happens if 2 idle codes are detected before a valid esd has been received or descramble synchronisation is lost during packet reception. the states of rx_dv and rx_er are summarised in figure 4. rx_er is clocked on the falling edge of rx_clk, and will remain active for at least 1 period of rx_clk. rx_dv rx_er rxd [3:0] indication 0 0 0000 through 1111 normal inter frame 0 1 1110 false carrier indication 1 0 0000 through 1111 normal data reception 1 1 0101 or 0110 data reception with errors figure 4. 100mb/s receive error states controls initialization, mode selection and other options are governed by the control inputs and register as described in the following paragraphs. tx_en tx_er txd [3:0] indication 0 x ignored normal inter frame data 1 0 0000 through 1111 normal data transmission 1 1 0000 through 1111 transmit error propagation figure 3. 100mb/s transmit error states initialization (reset_n) the NWK933 incorporates a power-on-reset circuit for self-initialization on power-up. during initialization the open-drain reset_n pin is driven low and all data outputs are disabled to prevent spurious outputs to the twisted-pair and to the mii interface. reset_n will remain low until the power supply has been stable for at least 400ns. the NWK933 will then release reset_n allowing the external pull-up to pull the pin high. device initialisation will not commence until reset_n is high. this allows the user to extend the inactive period by externally holding reset_n low. it will not normally be necessary for the user to reset the NWK933 because it is designed to automatically recover from fault conditions. however, if required, the user may initialize the device by doing a hardware or software reset. reset mode there are two types of reset in the NWK933 - hardware and software. the hardware reset is activated by setting the reset_n pin to logic 0, and holding it low for at least 100ns. this mode causes an over-all reset in the NWK933 - both analog and digital circuitry are reset. whilst reset_n is low, the spdst and fdst pins are inputs, and are used to determine the speed and duplex capability which will be advertised during auto-neg. a low on spdst advertises 100m capability. a high on fdst advertises full duplex capability. the software reset is activated by setting bit 15 in register 0 high. this bit is a self clear bit and causes a partial reset of the device. figure 5 summarises the different blocks to be reset and which reset will affect them: block hw reset sw reset management register yes yes pcs state machine (rcv, yes yes xmt, aneg) xmt scrambler yes yes rcv scramble yes yes control state machine yes no analog yes no figure 5. effects of reset note: holding reset_n low will hold the device in a static, low power state.
6 NWK933 low-power mode this function is set via the management interface. using mdc and mdio, bit 11 of register 0 is written high to put the NWK933 into low-power mode. the type of low power mode is dependant on bits 14 and 15 in register 24. for 24[15:14] = 0:0 the 10base-t and 100base-tx transceivers are disabled. the oscillator continues to run. both rx_clk and tx_clk are stopped, the rxd bus is held low and txd, txen, and txer are ignored. mdc and mdio are still active for new commands. this mode is intended to conserve power when the network connection is not required and the txop/txon output is undriven. typical current consumption is less than 10ma. for 24[15:14] = 0:1, everything is turned off, including the voltage references and the oscillator. this mode must be exited via the management interface. typical current consumption is 0.5ma. for 24[15:14] = 1:0, the only function available is the signal detect. the NWK933 will detect a signal amplitude on the cable and activate the interrupt. mint can be selected as either an active low or high interrupt. typical current consumption is less than 10ma. for 24[15:14] = 1:1, the NWK933 will automatically power down into a sleep mode if no activity is seen on the cable for approx 2 seconds. power up is also automatic if activity is seen. typical current consumption is less than 10ma. loopback mode diagnostic loopback may be selected at any time by asserting setting bit 14 in register 0. in 10base-t mode transmission to the txop/ txon output will be stopped and the rx10 clock recovery will receive input from the tx10 transmit path rather than from the rxip/rxin inputs. in 100base-tx mode transmission to the txop/txon output will be stopped and the rx100 clock recovery will receive input from the tx100 transmit path. repeater mode the NWK933 can be put into repeater mode by setting register 24 bit 0 high. in this mode, the crs will be active on receive only. in 100mbps repeater mode, the NWK933 is able to perform a disconnect function from the mii. this function is enabled by bit 1 in register 24. (note that if the device is not in repeater mode, this bit has no effect). the NWK933 will disconnect from the mii if it receives two consecutive false crs events with no good frame in between them or if a false crs event is longer then 480 +/- 4bt. if the NWK933 receives a good carrier event (480 +/- 4bt) or a good idle event (idle symbols for a period of 25000 to 30000 bit time) it will resume frame transfer to the mii. a false crs event happens if, at the beginning of a carrier event, the jk symbols are not received correctly. when the NWK933 is in 100m mode it will count all false crs events in register 27 bits 7:0. this counter is self cleared upon read. if a disconnect event occurs between the consecutive reads of register 27, bit 15 in the register will set high. auto-negotiation enable (anen) auto-negotiation may be hardware disabled by setting the anen pin to logic zero. during operation, auto- negotiation can be disabled by setting the anen pin low or by setting bit 12 of register 0 to zero. if auto- neg is disabled, the NWK933 will lose the link, and link will be re-established only after the NWK933 control state machine has determined the speed using bits 13 and 8 of register 0 to determine speed and duplex respectively. mii management interface, mdc and mdio the management interface is a 2 wire serial interface connecting a phy to a management entity. the management unit controls the phy and gathers information on the status of the phy. it does this via the implemented registers using mdc to clock the data on the mdio pin. link status change interrupt, mint mint is, by default, an active low interrupt which is activated whenever a change in the link status occurs. it can be changed to be active high by setting bit 13 in register 24. the interrupt will remain active until the controller acknowledges the interrupt by writing to register 21 (any data). should one or more link status changes occur between the assertion of mint and an ackowledge, then mint will be deasserted and then reasserted (deassertion time between 100ns and 150ns). only a single interrupt event may be queued at any one time. multiple status changes between an ackowledge will generate only a single queued interrupt.
7 NWK933 tx100 scrambler framing & control tx10 pulse shaper tx10 driver rx10 filter & signal detect rx100 & signal detect tx100 driver osc power on reset controls txd3-0 tx_er tx_en tx_clk crs col tx100ref tx10ref txop txon rxop rxon refclk xtal1 xtal2 reset_n anen mdc mdio pa4-0 mint manchester encoder tx10 clock gen. link pulse & manchester decode rx10 clock & data recovery framing & control framing & 5b4b decode aligner & descramble rx100 clock & data recovery rx100 equalizer & blw rxd3-0 rx_er rx_dv rx_clk framing &4b5b encode tx100 piso & encoder tx100 clock gen. leds aneg logic actst lnkst colst fdst spdst internal clock figure 6 NWK933 block diagram
8 NWK933 pin list pin # name type description md interface 20 rxin input differential receive pair from magnetics (-) 19 rxip input differential receive pair from magnetics (+) 28 txon output 100 differential transmit pair to magnetics (-) 23 txop output 100 differential transmit pair to magnetics (+) 35 txref10 input 10base-t transmitter current setting pin 36 txref100 input 100base-tx transmitter current setting pin 14 resetn ioput active low, power on reset output and external reset input 41 xtal1 input 25mhz crystal input 40 xtal2 input 25mhz crystal input mii interface 46 mdc input management interface clock (up to 2.5mhz) 45 mdio ioput management data 53 rx_clk output receive clock (2.5mhz for 10, 25mhz for 100) 55, 56, 57, 58 rxd0, rxd1, output receive data mii interace rxd2, rxd3 51 rx_dv output receive data valid. active high. 59 rx_er output receive error. active high. (rxd4 in symbol mode) 43 refclk input reference clock 64 tx_clk output transmit clock (2.5mhz for 10, 25mhz for 100) 60, 61, 62, 63 txd0, txd1, input transmit data mii interface txd2, txd3 4 tx_en input transmit enable. active high. 2 tx_er input transmit error. active high. (txd4 in symbol mode) 50 crs output carrier sense signal. active high. 49 col output collision signal. active high. 22 anen input auto negotiation enable. active high. 48 mint output mii interrupt control. 6 actst output receive / transmit active indication (led interface). active low. 7 colst output collision active indication (led interface) active low. 11 fdst ioput full duplex indication when reset_n high (led interface). active low. input when reset_n is low. high input means 933 advertises full duplex capability. 5 lnkst output link ok indication (led interface). active low. 12 spdst ioput speed indication when reset_n high (led interface). high for 100mb/s mode. input when reset_n is low. low input means 933 advertises 100mb/s capability. 31, 30, 29, pa0, pa1, input phy address 17, 13 pa2, pa3, pa4
9 NWK933 general the following is the register set that is implemented in the NWK933 device: the interface to these registers is via the mdc and mdio signals. the address of the NWK933 is specified by the pa<4:0> static inputs the md command is issued by the controller and can be read or write: command preamble start data op code phy address reg number ta data read 32 bits of 1 01 10 5 bits 5 bits z0 16 bit from phy write 32 bits of 1 01 01 5 bits 5 bits 10 16 bit from mac sc = self clear ro = read only rw = read or write ll = latch low until register read lh = latch high until register read register set reg 0 - control register bit bit name description default r/w 0.15 reset 1 = phy reset 0 rw 0 = normal operation sc 0.14 loopback 1 = loopback mode active 0 rw 0 = normal operation 0.13 speed 1 = 100 mbps 1 rw selection 0 = 10 mbps 0.12 aneg 1 = enable aneg process 1 rw enable 0 = disable aneg process 0.11 power down 1 = power down active 0 rw 0 = normal operation 0.10 isolation 1 = isolation in process 0 rw 0 = normal operation 0.9 restart 1 = restart the aneg process 0 rw aneg 0 = normal operation sc 0.8 duplex 1= full duplex mode 1 rw selection 0 = half duplex mode 0.7 collision 1 = collision test active 0 rw test 0 = normal operation 0.6:0 reserved write as 0 ignore on read.
10 NWK933 reg 1- status register bit bit name description default r/w 1.15 100baset4 1 = phy able to perform 100baset4 0 ro 0 = phy not able to perform 100baset4 1.14 100base-tx 1 = phy able to perform 100base-tx 1 ro - fdx 0 = phy not able to perform 100base-tx 1.13 100base-tx 1 = phy able to perform 100base-tx 1 ro - hdx 0 = phy not able to perform 100base-tx 1.12 10base-t 1 = phy able to perform 10base-t 1 ro - fdx 0 = phy not able to perform 10base-t 1.11 10base-t 1 = phy able to perform 10base-t 1 ro - hdx 0 = phy not able to perform 10base-t 1.10 100baset2 1 = phy able to perform 100baset2 0 ro - fdx 0 = phy not able to perform 100baset2 1.9 100baset2 1 = phy able to perform 100baset2 0 ro - hdx 0 = phy not able to perform 100baset2 1.8:7 reserved ignore when read 0 ro 1.6 mf preamble 1= phy accept management frames with short preamble 0 ro suppression 0 = normal preamble only 1.5 aneg 1 = aneg process completed 0 ro complete 0 = aneg process not completed or not active 1.4 remote 1= remote fault condition detected 0 ro fault 0 = no remote fault condition detected lh 1.3 aneg able 1 = phy is able to perform aneg 1 ro 0 = phy is not able to perform aneg 1.2 link status 1= link is up 0 ro 0 = link is down ll 1.1 jabber 1 = jabber condition detected 0 ro detect 0 = normal operation 1.0 extended 1 = extended register capability 1 ro regs 0 = no extended registers reg 2/3- NWK933 identifier register bit bit name description default r/w 2.15:0 oui mitel oui bits 0282 ro 3.15:0 oui/device id mitel oui bits and device code 1c7x ro
11 NWK933 reg 4- aneg advertisement register bit bit name description default r/w 4.15 np next page able - the NWK933 is not able to 0 ro perform next page 4.14 reserved 0 ro 4.13 remote fault 0 = no remote fault detected 0 r/w 1= a remote fault been detected 4.12:10 reserved 0 r/w 4.9:5 technology t4, 100fdx, 100hdx, 10fdx, 10hdx 0f r/w 4.4:0 selector 01 r/w field reg 5- aneg link partner ability register bit bit name description default r/w 5.15 np partner is next page capable 0 ro 5.14 ack partner sent an acknowledge bit 0 ro 5.13 remote fault partner detected a remote fault 0 ro 5.12:5 ability partners technology ability 0 ro 5.4:0 selector field partner selector field 0 ro reg 6- aneg expansion register bit bit name description default r/w 6.15:5 reserved 0 ro 6.4 parallel 0 = aneg process finished. no fault detected 0 ro detect fault 1 = a fault has been detected lh 6. 3 link partner 0 = link partner is not next page able 0 ro next page able 1 = link partner is next page able 6.2 next page 0 = NWK933 is not able for next page 0 ro able 6.1 page 0 = no new page been received 0 ro received 1= a new page has been received and is in reg 5 lh 6.0 link partner 0 = link partner is not aneg able 0 ro aneg able 1 = link partner is aneg able reg 16, 17, 18, 19, 20 - test registers bit bit name description default r/w 15:0 reserved test mode only 0000 res
12 NWK933 reg 21 - mii interrupt control register bit bit name description default r/w 21.15:0 clear interrupt write any data pattern to clear mint 0 wo reg 22, 23 - test registers bit bit name description default r/w 15:0 reserved test mode only 0000 res reg 24- NWK933 specific register bit bit name description default r/w 24.15:14 pwrcon[1:0] low power controls: 00 rw 00 = full receive path active. no transmit. 01 = deep sleep (all off including vref & osc) 10 = sleep (generate mii interrupt on activity) 11 = auto shut down, auto wake on activity 24.13 mintpol 1 = mint output active high 0 rw 0 = mint output active low 24.12 pol dis 1 = disable 10base-t autopolarity correction 0 rw 24.11 sqe disable 1 = disable sqe in 10base-t half duplex mode 0 rw 24.10 jab disable 0 = in case of jabber the 10base-t will cut the 0 rw transmitted frame (normal operation) 1 = jabber function disable 24. 9 loop 10 1 = enable mii loopback in 10base-t half duplex mode 0 rw 24.8 force rx force receive regardless of link 0 rw 24.7 force tx force transmit regardless of link 0 rw 24.6 crs_ctl crs behavior in full duplex mode:- 0 rw 0 = crs is active for transmit only 1= crs active for receive or transmit 24.5 mf 1 = mdio data accepted without preamble 0 rw 24.4 byp align 0 = normal operation 0 rw 1 = bypass the aligner function 24.3 byp enc 0 = normal operation 0 rw 1 = bypass the 4b5b encoder function 24.2 byp scr 0 = normal operation 0 rw 1 = bypass the scrambler function 24.1 discen 0 = disable disconnection events 0 rw 1 = enable disconnect on false carrier detection 24:0 rptr set repeater mode (affects crs generation) 0 rw
13 NWK933 reg 25 - aneg status bit bit name description default r/w 25.15:14 reserved test mode only - do not set high 0 ro 25.13 pol 1 indicates polarity reversal on rx inputs (10base-t) 0 ro 25.12:8 pa copy of phy address pins pa<4:0> ro 25.7 aneg 1 = aneg completed 0 ro complete 0 = aneg did not complete (same as reg1.5) 25.6 duplex aneg result - duplex operation 0 ro 0 = hdx, 1 = fdx 25.5 speed aneg result - speed of operation 0 ro 0 = 10m, 1 = 100m 25.4 ability mtc 1 = abilities match between registers 4 & 5 0 ro 25.3:0 aneg state aneg state machine current state 0 ro reg 26 - symbol error counter bit bit name description default r/w 26.15:0 rx_err number of rx_err events since last read - clears 0 ro counter either in change of speed or read of this reg. sc reg 27 - false carrier event counter bit bit name description default r/w 27.15 disconnect the disconnect mechanism status 0 ro lh 27.14:8 reserved 0 ro 27.7:0 false crs number of false crs events since last read. 0 ro counter active only when discen = 1. sc reg 28, 29, 30, 31 - test registers bit bit name description default r/w 15:0 reserved test mode only 0000 res
14 NWK933 operating conditions supply voltage +3.0v to 3.6v ambient temperature 0 c to +70 c dc electrical characteristics recommended operating conditions apply except where stated. characteristic symbol value units conditions min max dc parameters - input high level input voltage v ih 2v dd v low level input voltage v il v ss 0.8 v high level input current i ih -1 m a low level input current i il -C1 m a no pull up pin capacitance to ground - 8 pf including package dc parameters - output -6ma buffers high level output voltage v oh 2.4 v dd v low level output voltage v ol v ss 0.4 v high level output current i oh -C6ma low level output current i ol -6ma rise time - 4 ns 0.4v to 2.4v into 20pf load fall time - 4 ns 0.4v to 2.4v into 20pf load pin capacitance to ground - 8 pf differential output peak differential voltage 2.2 2.8 v 10mbs mode high level 0.95 1.05 v 100mbs mode zero level -0.05 0.05 v 100mbs mode low level -1.05 -0.95 v 100mbs mode note: differential outputs are 802.3 compliant ac electrical characteristics recommended operating conditions apply except where stated. characteristic symbol value units conditions min max differential output baseline to +vout 3 5 ns 100mbs mode baseline to -vout 3 5 ns 100mbs mode +vout to baseline 3 5 ns 100mbs mode -vout to baseline 3 5 ns 100mbs mode note: differential outputs are 802.3 compliant
15 NWK933 ac electrical characteristics (continued) recommended operating conditions apply except where stated. characteristic symbol value units conditions min max refclk frequency 25 100ppm mhz duty cycle 45 55 % rxclk frequency 25 100ppm mhz 100mbs mode duty cycle 40 60 % 100mbs mode frequency 2.5 100ppm mhz 10mbs mode duty cycle 40 60 % 10mbs mode txclk frequency 25 100ppm mhz 100mbs mode duty cycle 40 60 % 100mbs mode frequency 2.5 100ppm mhz 10mbs mode duty cycle 40 60 % 10mbs mode mdc frequency - 2.5 mhz minimum high/low 160 - ns supply current typ max 10 base-t idle 80 90 ma measured at 3.3v 10 base-t active 180 200 ma room temperature 100 base-t idle 128 145 ma these figures include 100 base-t active 133 150 ma the current flowing sleep mode 5 6 ma in the transmit resistors deep sleep mode 0.25 1 ma resetn = 0 1 2 ma
16 NWK933 figure 7 external components external components connecting an external 25mhz reference if an external clock is used then it should be driven into the refclk input, and xtal1 must be connected to ground. xtal2 must be left unconnected. if a crystal is used, refclk must be connected to ground. resetn pull-up resistor this resistor is required regardless of whether or not resetn is used externally. rx input decoupling the method of using a split input load resistor and de-coupling the centre tap reduces common mode noise. crystal oscillator for ieee802.3 compliance the oscillator must run at 25mhz 100ppm. the NWK933 on-chip circuitry contributes less than 40ppm variability to the oscillator frequency, therefore the crystal must be specified to 60ppm. this must include variations due to temperature and ageing. the crystal must be capable of dissipating 0.5mw of power. external capacitors are required on the xtal1 & xtal2 pins. manufacturer's recommendations should be followed. tracking to the crystal and the capacitors must be as short as possible. other signal paths must not cross the area. the NWK933 is supported by the following magnetics: vendor magnetics pulse h1119 tx_clk txd3 txd2 txd1 txd0 rx_er rxd3 rxd2 rxd1 rxd0 dvdd2 rx_clk dgnd2 rx_dv crs col pa3 rxgnd1 rxip rxin rxvdd1 anen txop txvdd2 txgnd2 txgnd1 txvdd1 txon pa2 pa1 pa0 subgnd1 subgnd2 tx_er dgnd1 tx_en lnkst actst colst dvdd1 rxvdd3 rxgnd3 fdst spdst pa4 resetn rxvdd2 rxgnd2 5k(5%) 10k(5%) vdd vdd vdd vdd vdd vdd mint dvdd3 mdc mdio dgnd3 refclk oscvdd xtal1 xtal2 oscgnd txcgnd4 txvdd4 txref100 txref10 txvdd3 txgnd3 25mhz c2 c2 1.24k 1% 1.24k 1% 24.9 (1%) 24.9 (1%) 10 0.01 f 30 (1%) 30 (1%) 20 (1%) 20 (1%) 0.01 f rxop rxon txin txic txip 1: 2 magnetics

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